1. Field
Some embodiments of the present disclosure relate generally to memory bandwidth management, and may also relate to a high-bandwidth memory (HBM) system including a processor and a memory controller on a HBM logic die, and to methods of processing in the HBM.
2. Description of the Related Art
FIG. 1 is a block diagram of a high-bandwidth memory HBM+ system.
Referring to FIG. 1, a conventional HBM system may generally use a single master, which is generally an off-HBM memory host controller that is used to control a corresponding memory.
In a HBM+ system 100, however, a single slave (e.g., a main memory, which may be a volatile memory, such as a dynamic random access memory (DRAM) on a DRAM die) 110 may have two memory controllers 120 as masters. The two masters may be an off-HBM memory controller 120a, and an on-HBM memory controller 120b that is located on the HBM logic die 140 of the HBM 160. The HBM logic die 140 may correspond to a bottom layer of a 3D-stack memory that is the HBM 160, while the DRAM die 110 may correspond to one of the upper layers of the HBM 160. The HBM logic die 140 may control the DRAM die 110 using a “near” memory controller (NMC) 120b, which may be instructed by a processor (PU) 170 to control the DRAM die 110.
The off-HBM memory controller 120a may be referred to as a host memory controller 120a (e.g., a host memory controller 120a of a central processing unit (CPU), a graphics processing unit (GPU), or an accelerated processing unit (APU) 130). The on-HBM memory controller 120b may be referred to as a coordinating memory controller 120b, and may be located on the HBM logic die 140.
The host memory controller 120a may also be thought of as a remote memory controller, or as a “far” memory controller (FMC), because it is remotely located at a position that is farther away from the DRAM die 110 than the coordinating memory controller 120b. The coordinating memory controller 120b may be thought of as a local memory controller, or a “near” memory controller (NMC) 120b due to its proximity to the DRAM die 110. It should be noted that either or both of the host memory controller 120a and the coordinating memory controller 120b may be represented by a general memory controller.
Furthermore, the host memory controller 120a and the coordinating memory controller 120b may communicate asynchronously. Accordingly, a problem may arise when both the host memory controller 120a and the coordinating memory controller 120b attempt to concurrently access the DRAM 110.
A potential solution to conflicts arising from attempted concurrent access by both of two different memory controllers in other arts (e.g., in a system-on-a-chip (SoC) using a transaction-based protocol, such as advanced extensible interface (AXI)) may include using a bus arbiter as a central arbiter/centralized controller. The bus arbiter may decide which bus master will be allowed to control the bus for each bus cycle, and may track the status of all components. Accordingly, the two different memory controllers may ask the bus arbiter for permission to access memory, and the bus arbiter may grant permission to one of the memory controllers (i.e., granting access to only a single master at a time to enable communication between the selected master and the slave without interference from the non-selected master). Thereafter, the selected memory controller, which is granted access, may access the memory, and/or the memory can respond to the memory controller.
However, the above potential solution is not applicable to the HBM+ system 100. Unlike a transaction-based protocol, HBM does not support handshaking operations, meaning that there is no feedback signal from the HBM 160 to any memory controller 120. Further, the HBM logic die of a conventional HBM is unable to perform compute functions exclusively within the HBM logic die.
Also, unlike a transaction-based protocol, HBM does not support non-deterministic timing, meaning that once the host memory controller 120a sends a request to the HBM 160, the host memory controller 120a expects the HBM 160 to respond in a deterministic amount of time. That is, if one of the memory controllers 120 sends out a command or a request, then the HBM 160 must respond within a given amount of time (e.g., within about thirty nanoseconds) to ensure that the HBM 160 is properly providing the requested data.
The above information is only for enhancement of understanding of the background of embodiments of the present disclosure, and therefore may contain information that does not form the prior art.